Structure and method for formation of a bipolar resistor

ABSTRACT

A process of forming a nitride film on a semiconductor substrate including exposing a surface of the substrate to a rapid thermal process to form the nitride film.

FIELD OF THE INVENTION

The present invention relates to a resistor structure for semiconductordevices and a method of forming the resistor structure. In particular,the present invention relates to a structure for formation of a blockedsilicide resistor and a method of forming the structure. The presentinvention also relates to a silicon nitride film. Additionally, thepresent invention concerns a bipolar transistor structure and method offabricating the bipolar transistor structure.

BACKGROUND OF THE INVENTION

Circuit components are part of every semiconductor device structure. Forexample, resistors, capacitors, and other such structures are typicallyformed on a semiconductor substrate. However, processes for formation ofthe circuit components are not always compatible with the semiconductordevices formed in and on the semiconductor substrate. Also, as newsemiconductor device structures come into existence, existing structuresof circuit components and methods of forming the circuit components arenot always compatible with the structures of the semiconductor devices.For example, methods for formation of circuit components on asemiconductor substrate may cause alterations to the materials andstructures of semiconductor devices previously created in and on asemiconductor substrate.

SUMMARY OF THE INVENTION

The present invention concerns a process of forming a nitride film on asemiconductor substrate including exposing a surface of the substrate toa rapid thermal process to form the nitride film.

Additionally, the present invention relates to a method of forming aresistor. Silicide formation is selectively blocked over a dopedpolycrystalline silicon region or doped silicon region by forming aregion of a silicon nitride film utilizing a rapid thermal chemicalvapor deposition (RTCVD) silicon nitride deposition process afterformation of device source/drain implants and completion of activationanneals. A contact is formed on either side of the blocked region toform a current path through the blocked region.

Also, the present invention provides a blocked silicide resistorstructure. A silicide blocking region including a silicon nitride filmis arranged over a region of polycrystalline silicon or doped silicon.The silicon nitride film has been formed by a RTCVD nitride depositionprocess. A region of a silicide is adjacent opposite sides of thesilicon nitride film. A contact overlies each of the adjacent silicideregions. The resistor overlies device source/drain implants.

Furthermore, the present invention also provides a bipolar transistorstructure that includes a nitride barrier layer formed by a RTCVDnitride deposition and a CMOS FET structure including a conformalnitride barrier film formed by a RTCVD silicon nitride depositionprocess.

Still other objects and advantages of the present invention will becomereadily apparent by those skilled in the art from the following detaileddescription, wherein it is shown and described only the preferredembodiments of the invention, simply by way of illustration of the bestmode contemplated of carrying out the invention. As will be realized,the invention is capable of other and different embodiments, and itsseveral details are capable of modifications in various obviousrespects, without departing from the invention. Accordingly, thedrawings and description are to be regarded as illustrative in natureand not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

The above-mentioned objects and advantages of the present invention willbe more clearly understood when considered in conjunction with theaccompanying drawings, in which:

FIG. 1 represents a cross-sectional view of a known structureillustrating the effects of precleaning on the structure;

FIG. 2 represents a cross-sectional view of an embodiment of a structureaccording to the present invention illustrating the effects ofprecleaning;

FIG. 3 represents an embodiment of a processing chamber that may beutilized to carry out a process according to the present invention;

FIGS. 4-6 represent cross-sectional views of an embodiment of a bipolartransistor structure according to the present invention at variousstages of an embodiment of a process according to the present inventionfor forming the structure;

FIG. 7 represents a cross-sectional view of an embodiment of a conformalnitride barrier layer according to the present invention;

FIG. 8 represents a photomicrograph that illustrates a nitride layerformed according to an embodiment of a known process;

FIG. 9 represents a photomicrograph that illustrates a nitride layerformed according to another embodiment of a known process;

FIG. 10 represents a photomicrograph that illustrates a conformalnitride layer formed according to an embodiment of a process accordingto the present invention; and

FIG. 11 represents a photomicrograph that illustrates a conformalnitride layer formed according to another embodiment of a processaccording to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

As discussed above, formation of circuit components can alter thematerials and/or the structures of semiconductor device structures formin and on a semiconductor substrate. For example, high temperatures mayalter previously carried out source/drain implants. Additionally, stepsthat might typically be carried out can alter the structure of thecircuit component or a structure formed as part of a process of creatinga circuit component.

According to one particular example, a blocked silicide resistorstructure is formed by locally blocking silicide formation. This caninvolve blocking any silicide formation. Typically, the silicide is ametal silicide. Examples of typical metal silicides include titaniumsilicide, cobalt silicide, and platinum silicide. The silicide formationis blocked over a region of doped silicon or doped polycrystallinesilicon, typically referred to a poly or poly-Si. After blockingsilicide formation, creating a blocked silicide resistor can includepositioning a contact on either side of the region with the blockedsilicide to form a current path through the resistor.

As referred to above, formation of electric circuit elements can includeprocesses incompatible with maintaining the integrity of existingsemiconductor device structures previously formed in and on asemiconductor substrate. Also, processes necessary for furtherprocessing of structures on a semiconductor substrate may beincompatible with structures formed as part of the circuit components.In the example of the blocked silicide resistor, in standard siliconbased or silicon-germanium based semiconductor technologies, theformation of the blocked silicide resistor occurs late in the front endof line (FEOL) process, after completion of device source/drain (S/D)implants and activation anneals. This means that the blocked silicideresistor process must be accomplished with minimal thermal budget so asnot to upset the existing devices.

This is particularly important because the blocked silicide resistor istypically offered as an option for in particular device structures. If anitride deposition process were utilized that caused shifts in FEOLimplants, then a wafer processed with a blocked silicide resistorprocessing typically would not have the same transistor characteristicsas a wafer processed without the blocked silicide resistor processing.This, then, would mean that the same technology models typically couldnot be used for wafers with and without the blocked silicide resistoroption, thus making such a device impractical as a technology option.Therefore, the present invention provides an important efficiency withrespect to marketing and manufacturing concerning the issue of notaltering existing devices.

Silicon nitrides are good choices as a silicide blocking film because oftheir easy integration with the salicide process. However, because thethermal budget is constrained by the prior carrying out of source/drainimplants and activation anneals, conventional low pressure chemicalvapor deposition (LPCVD) nitride deposition is not acceptable. Thecurrent solution has been to use Plasma Enhanced Chemical VaporDeposition (PECVD) of the silicon nitride.

However, PECVD nitride has other associated problems. For example, whilePECVD nitride is formed at a suitably low temperature, PECVD nitridefilms are generally of lower density, and contain a significant amountof hydrogen. Consequently, HF based salicide precleans are prone toremove large amounts of the PECVD nitride, undermining its effectivenessas a silicide block.

Furthermore, technologies based on titanium silicide are able to useheavily buffered HF solutions that have a lower etch rate of PECVDnitride. However, cobalt silicide technologies require lightly bufferedor dilute HF pre-cleans that have an excessive PECVD nitride removal.

An additional disadvantage of the known PECVD silicide blocking processis that the PECVD film does not tend to be very conformal. Along theselines, sidewall depositions are typically about 60% to about 80% thethickness of horizontal surface depositions. This means that when thesilicide blocking PECVD nitride is etched to clear horizontal surfaces,spacer nitride films that are underneath the PECVD silicide blockingnitride on the sidewalls of gates will be etched by the silicideblocking nitride etch process. As a result, these nitride films will bepulled down, making the spacer structure less robust at forming asalicide structure.

Nitride films also find importance in bipolar transistor structures.Often, the nitride layers are utilized as barrier layers. As withcontext described above, formation of the nitride layer can also alterexisting structures in a substrate.

As described above, processing associated semiconductor devicesformation processes may also conflict with the formation of circuitcomponents. Along these lines, an aggressive preclean process typicallyrequired for cobalt silicide etches the currently used PECVD nitride somuch that the film can no longer be used to reliably block silicideformation. FIG. 1 illustrates this problem.

Along these lines, FIG. 1 illustrates where a region 1 of PECVD nitridewas formed prior to a preclean process. After the preclean process, thenitride was discontinuous as represented by nitride regions 3. As aresult, formation of silicide regions 5 occurred in the region theirformation should have been blocked. Silicide regions 7 are arranged onopposite sides of the region where silicide formation is to be blocked.A contact 9 has been formed over each silicide region 7.

An alternative to PECVD processes includes conventional furnace lowpressure chemical vapor deposition (LPCVD) processes for nitridedeposition. Although the films created with LPCVD may have better filmquality and would therefore not be etched by the preclean, LPCVDrequires a long process cycle time, on the order of about two to aboutthree hours, at temperatures of about 720° C. or higher. For this reasonblocked silicide resistors cannot be made by this method without a majorredesign of the device to allow for this extra thermal budget or withoutthe silicide block resistor as an option in a technology.

Nitride films may be deposited in other applications. For example, LPCVDnitride films may be deposited processes for forming bipolartransistors. In such cases, it is desirable to reduce the thermal cycleto reduce outdiffusion of the boron profile of the structure.

Nitride films are useful in general after carrying out the “front end ofline” (FEOL) process steps, such as steps utilized to create thin filmstructures that form transistors. Along these lines, it is typicallyrequired to deposit a capping nitride layer. This capping layer, oftenreferred to as a “barrier nitride”, acts as a diffusion barrier for“back end of line” (BEOL) and “middle of line” (MOL) metal materials andassociated contaminants that are used for device contacting and contactformation processing.

The barrier layer may also provide integration advantages for formationof a first layer of contacts. The contact typically must come down andcontact structures of different heights. Such structures can includediffusion regions, poly-silicon gates, and/or the different structuresof a bipolar transistor, such as reach-through contact, base contact,and emitter contact, all of which are also at different heights.

Since the fill material over the barrier nitride is typically a dopedglass material, an etch that stops on nitride can be used to etch downthe structures that are of different heights. Then, a nitride etch canbe used to etch through the nitride. In this case, the nitride typicallyhas a consistent thickness everywhere.

State of the art thin film processing for barrier nitride creationtypically utilizes plasma enhanced chemical vapor deposition (PECVD)processing. Two different process regimes have been explored. Accordingto one regime, the deposition of the process is carried out at about480° C. The other regime involves a slightly improved process where thedeposition is carried out at 550° C. With both of these processes,however, conformality of the deposited film is non-ideal, withsignificantly less deposition on vertical structures than on horizontalstructures.

Conformality of the barrier nitride over shallow trench isolation (STI)regions is a major consideration in a properly designed diffusioncontact. Poor conformality over the STI divot has been shown tocontribute to high parasitic leakage current from contact plug tosubstrate. Typically, this arises when a partially landed contact holeis etched, causing punch-thru into the isolation through the thinbarrier nitride over the STI divot, the dip in the STI fill materialthat is found near the edge of the isolation trench. Subsequent contactfill results in a parasitic contact to the well or substrate in place ofthe desired ohmic contact to diffusion.

The present invention utilizes enhancements in rapid thermal processingtechnology, employing a rapid thermal chemical vapor deposition (RTCVD)process that takes place at temperatures similar or the same as astandard batch furnace. However, RTCVD processes according to thepresent invention include very short times at peak temperature. Theprocess of the present invention may be utilized in any of the aboveapplications or any other application.

In the case of silicon nitride, the present invention makes use of rapidthermal nitride deposition processes that can deposit films on the orderof about 35 Å to about 400 Å with a total exposure to temperatures above700° C. of 2 minutes or less. Also, the film quality and hydrogencontent of these RTCVD nitride film according to the present inventionis significantly better than that of PECVD nitride films. The short timeat high temperature according to the processes of the present inventionallows such a process to be implemented without causing excess diffusionof device implants.

Unlike a PECVD deposited film, an rapid thermal chemical vapordeposition (RTCVD) film according to the present invention resists thepreclean, having a low etch rate in lightly buffered hydrofluoric acid(HF). Also, unlike LPCVD, a film according to the present invention hasa short time at the maximum temperature. Also, a film according to thepresent invention will allow for the construction of a blocked silicideresistor on cobalt silicide technologies without any alteration of thedevice.

In terms of thermal budget, LPCVD>RTCVD>PECVD. In other words, LPCVD hasthe greatest thermal budget and PECVD the lowest. However, in terms ofHF etch rate, PECVD>RTCVD>LPCVD. So, the LPCVD film is the most denseand from a film quality standpoint may potentially represent the bestquality nitride. However, the device cannot withstand the thermal budgetrequired by LPCVD, which has the greatest thermal budget as shown above.RTCVD may be thought of as basically in the middle of the two andproviding an acceptable result for both items. In terms of conformality,LPCVD=RTCVD>PECVD. Therefore, with respect to conformality, RTCVD is notin the middle and far surpasses PECVD capabilities.

In other contexts, the present invention can produce other benefits. Forexample, using a RTCVD nitride barrier layer to replace a nitridebarrier layer deposited by LPCVD reduces the exposure to elevatedtemperatures of a substrate and structures formed therein and thereon.Along these lines, RTCVD nitride films according to the presentinvention, typically deposited at temperatures described herein, havedry and wet etch rates comparable to LPCVD nitride films. However, thethermal cycle required to deposit a film having a specified thickness isgreatly reduced with processes according to the present invention.

Future generations of SiGe hetero-junction bipolar transistors (HBTs),after the insitu boron doped SiGe base been deposited, the less exposureto elevated temperatures, or thermal cycling, the device experiences,the less outdiffusion of the boron profile the device will undergo.Generally, the lesser the outdiffusion, the faster a device will run.Also, for future scaling purposes, an RTCVD nitride film of about 100 Åto about 150 Å will be required with good thickness uniformity anddensity and which maintains good film integrity under high pressureoxidation, dry etch, and wet etch. Such a film will be valuable toprotect the base and to control the emitter size.

In accordance with the above, the present invention provides a processfor forming a silicon nitride film on a semiconductor substrate. Thesilicon nitride film provided a silicide formation blocking film. In thecontext of the present invention, the silicon nitride film is typicallyformed on a surface of a polycrystalline silicon region or doped siliconregion. The silicon nitride film is formed by exposing a surface of thepolycrystalline silicon region or doped silicon region to a RTCVDnitride deposition process.

A film according to the present invention may be formed at a temperatureof about 600° C. to about 850° C. According to one example, thetemperature is about 700° C. According to another example, thetemperature is about 775° C. Factors that can affect the temperaturethat the process is carried out at include the thermal budget. Alongthese lines, typically, the lower the temperature that the process maybe carried out at, the better, particularly with the silicide blockingresistor, bipolar transistor barrier nitride and transistor barriernitride discussed herein.

Typically, as the process temperature is lowered, sacrifice depositionrate is sacrificed. In other words, the reactions occur slower at lowertemperature. Therefore, while a deposition process might be carried outfor about a full 2 minutes at about 700° C., the same film thickness canbe deposited in about 1.5 minutes at about 775° C. Unfortunately, forthe examples of device structures described herein, such devicestypically cannot withstand processing at about 775° C. However, theinterrelationship between temperature and process speed is one reasonwhy the 680° C. process typically is currently utilized. It has beenfound that a temperature of about 700° C. process is the hottest processthat the device structures can withstand. Therefore, this represents thequickest possible process that can be carried out.

In the future, tooling may be developed that can conduct the process athigher pressures. This could permit the process to be carried out atabout 650° C. without significant loss of process speed. As a result,such a process will probably become highly utilized for RTCVD.

The period of time that the process exposes a substrate to the maximumtemperature may vary. Typically, the process is as the name implies,rapid. Along these lines, the period that the maximum temperature issustained may vary from about 30 seconds to about 5 minutes. Typically,the time is about 2 minutes or less. The period of time that the processis carried may depend upon the desired thickness of the film.

Sometimes, to improve the uniformity across a wafer of the deposition,thermal stabilization steps of about 30 to about 60 seconds may be addedto a process prior to reaction gases being flowed into the chamber.These thermal stabilization steps can allow the wafer to equilibrate toa more uniform temperature at all points. Then, when reaction gases areflowed, the reaction rate at all points will be correspondingly moreuniform. Typically, if thermal stabilization steps are included in aprocess, the length of the steps is minimized to help achieve gooduniformity and maximum tool throughput. It is conceivable, though, thatlonger thermal stabilization steps may be added that may increase therequired time at temperature.

Other process parameters that may be important in a process according tothe present invention include the pressure that the process is carriedout at. Along these lines, a process according to the present inventionmay be carried out at in a processing chamber the pressure in which maybe controlled. Along these lines, processes according to the presentinvention may be carried out at a pressure of about 50 torr to about 250torr. According to one particular example, the process is carried out ata pressure of about 100 torr.

Additionally, control of the conditions in the processing chamber mayinclude introducing gasses into the processing chamber while the processis being carried out. Examples of the gasses include silane (SiH₄),ammonia (NH₃), dichlorosilane (DCS), SiCl₂H₂, trichlorosilane (TCS)(SiCl₃H), and disilane (Si₂H₆). The amount of gas introduced into theprocessing chamber may vary. If silane and ammonia gasses are introducedinto the chamber they may be introduced at a ratio of about 40 sccmsilane to about 4 slm ammonia, or about 0.04:4. The rate that the gassesmay be introduced into the chamber may vary from about 1:50 to about1:400. According to one particular example, a ratio of about 1:200,SiH₄:NH₃ is utilized.

FIG. 3 illustrates an example of an apparatus that may be utilized tocarry out the present invention. The chemical vapor deposition apparatus100 illustrated in FIG. 3 includes a processing chamber. The chamber maybe lined with a quartz liner.

A substrate 105 to be processed is arranged within the processingchamber. Typically, the substrate is a semiconductor wafer. As statedabove, typically, the processing of the wafer has progressed to thepoint where source/drain implants and activation anneals have beencarried out. According to the present invention a single wafer or aplurality of wafers may be arranged within a processing chamber.

A substrate being processed in the chamber may be arranged on asusceptor 109. The susceptor 109 may be supported by support 111. Asindicated by arrow 113, the support, susceptor, and substrate beingtreated may rotate. Rotation is typically carried out in processing tohelp ensure uniformity of processing. The support, susceptor, andsubstrate may rotate at a speed of about 0 RPM to about 60 RPM.According to one particular example, the substrate rotates at a speed ofabout 35 rpm. However, the support, susceptor, and substrate may rotateat any rate to help ensure uniformity of processing.

The interior of the processing chamber may be heated with at least onelamp. Along these lines, at least one lamp may be arranged above and/orbelow the processing chamber. The embodiment illustrated in FIG. 3includes a plurality of upper lamps 115 arranged above the processingchamber as well as a plurality of lower lamps 117 arranged below theprocessing chamber.

Determining whether lamps should be provided above the processingchamber, below the processing chamber or both may depend upon how it isdesired the processing be carried out. Typically, the number andarrangement of lamps is designed to help ensure uniform heating of asubstrate and processing chamber and also to reduce gas phasenucleation. According to one example, 20 lamps are arranged above thesusceptor and 20 lamps are arranged below the susceptor.

The lamps both above and below the chamber may be arranged to furtherhelp ensure the desired processing characteristics. For example, in theembodiment described above, which includes 40 lamps, the lamps may bearranged in a circle having a diameter of about 200 mm. The lamps may befurther controlled by adjusting the direction that they face. Forexample, some lamps may be directed toward the center of the susceptorand some may be directed toward the periphery of the susceptor. Thelamps could also be directed anywhere between the center and theperiphery. According to one particular example, one-half of the lampsare directed toward the center of the susceptor and one-half toward theperiphery. The thickness uniformity produced may be tuned by adjustinglamp numbers, arrangement, direction, among other parameters.

The same process could be deposited in a different chamber thandescribed above. For example, an aluminum, cold wall chamber with aresistively heated susceptor could be used to achieve the same results.Electrically heated systems could also be utilized to heat chamber wallsor other walls to conductively heat the chamber.

A silicon nitride film formed according to the present invention mayhave any desired thickness. Typically, the film thickness is sufficientto provide the desired silicide blocking function. According to oneexample, the film has a thickness of about 100 Å or less. The processconditions may be controlled to result in formation of such a film.those of ordinary skill in the art, once aware of the present disclosurecould control the process to result in a desired film without undueexperimentation.

As discussed above, the present invention typically is carried out inthe context of forming a blocked silicide resistor, such as a silicideblocked resistor. Of course, the present invention may be utilized inany context. In the formation of a resistor, the RTCVD nitridedeposition may be carried out. Then, a contact may be formed on eitherside of a silicon nitride film. The contacts form a current path throughthe region where silicide formation has been blocked. Also, the materialthrough which the current path is driven typically is formed or dopedwith prior steps to provide the desired resistance.

The film may be formed with the thickness described above. Along theselines, the process may be carried out with the parameters, such astemperature, pressure, rotation, etc., described above. After formationof the silicon nitride film, a preclean may be carried out. The precleancan include exposing the silicon nitride film, as well as the entireupper surface of the semiconductor structure as exists after formationof the film, to a solution of hydrofluoric acid. The hydrofluoric acidmay be lightly buffered or dilute. Those of ordinary skill in the artwould know what strength acid to utilized without undue experimentationonce aware of the disclosure contained herein.

Utilization of such HF solutions is contrary to known processes thatrequire heavily buffered HF solutions to avoid damaging the siliconnitride film. Along these lines, a RTCVD nitride film according to thepresent invention is a higher quality film as compared to films formedaccording to the prior art. The films according to the present inventionresist preclean etching, and block all silicide formation in the regionof the resistor.

Making a PECVD film thicker to accommodate for the higher etch rate inprecleans, which results in the degradation illustrated in FIG. 1, isnot a favorable solution since it tends to increase the susceptibilityto gate-to-silicon leakage problems. Additionally, PECVD films have alower wet etch rate. However, they also have a fast rate of deposition,which requires thicker films to maintain thickness control. The presentinvention does not suffer from these shortcomings.

For example, films formed according to the present invention haveexcellent wet etch characteristics. In other words, the films will notbe easily removed by the wet etch steps. This permits formation of verythin films.

According to one example, the present invention permits an silicideblocked resistor to be formed having a thickness of about 120 Å in acobalt silicide product.

FIG. 2 illustrates one embodiment of a film according to the presentinvention. In FIG. 2, the broken line represents the surface of asilicon nitride layer 20 formed according to the present invention priorto carrying out a preclean process. At this point, the nitride layertypically has a thickness of about 100 Å to about 200 Å. After carryingout a preclean the nitride film 22 has been partially removed. Ascompared to the prior art film shown in FIG. 1, the film shown in FIG. 2has maintained its integrity to a much greater degree without anyportions entirely removed. Precleaning typically results in the loss ofa certain amount of the thickness. According to one example, the loss isabout 10 Å to about 50 Å.

FIG. 2 also shows silicide regions 24 and 26 on opposite sides of thenitride film 22. As stated above, silicide regions 24 and 26 may bemetal silicides including the specific examples listed above or anyother silicide. Contacts 28 and 30 extend up from the silicide regions24 and 26.

In the context of a nitride barrier structure in a bipolar transistor,after in-situ boron doped base deposition and a sacrificial oxidegrowth, an RTCVD barrier nitride film may be deposited according to thepresent invention in place of a LPCVD nitride as is currently carriedout. Subsequently, a polycrystalline silicon conversion layer, PECVDnitride region and tetraethyl ortho silicate (TEOS) oxide region may bedeposited. Next, the emitter pedestal may be defined by standardphotolithography and dry etch process steps. The extrinsic base sidewallmay then be defined. After the extrinsic base implant, the TEOS sidewallmay be striped. FIG. 4 illustrates the inventor at this stage of theprocess. Along these lines, FIG. 4 illustrates oxide layer 32, RTCVDnitride layer 34, conversion oxide layer 36, emitter pedestal space 38,filled with polycrystalline silicon 40 and PECVD nitride 42.

At this stage, the poly layer 36 may be converted to oxide grown onsilicon at reduced temperature and elevated pressure to increasereaction rate (HIPOX). Then, the PECVD nitride 42 may be removed. Theemitter may then be opened by etching away unconverted poly region 40and PECVD nitride 42 to result in the structure as shown in FIG. 5.

Subsequently, the portion of the sacrificial oxide layer 32 in theemitter region 38 may be removed by a wet etch. Emitter polycrystallinesilicon 44 may then be deposited to result in the structure shown inFIG. 6. With the RTCVD barrier nitride in place, the thermal cycle maybe reduced to a few minutes at a temperature of about 750° C. or about700° C., rather than the thermal cycle of about 30 minutes at about 720°C. for an LPCVD barrier nitride. In spite of this, the film maintainsgood integrity after high-pressure oxidation and dry and wet etches. Ofcourse, any of the temperatures, processing times and/or otherparameters described herein may be utilized in the deposition of theRTCVD nitride layer.

According to one particular embodiment, an RTCVD nitride layer wassubstituted for an LPCVD nitride layer in an NPN transistor. In thisapplication, key NPN transistor electrical parameters that may changedue to the RTCVD nitride are summarized in Table 1. As can be seen, thebase current and collector current or gain (Beta) of the transistorexperience little or no change. The intrinsic (50×50) and extrinsic(51×700) base-emitter junction capacitance showed very little variationas well. If, indeed, a delta exists, the RTCVD nitride thickness can beadjusted to yield the same capacitance as experienced with a LPCVDnitride. Also, as shown in Table 1, utilizing RTCVD increased the yieldfor the wafers with RTCVD nitride. TABLE 1 Key NPN Electrical Parametersfor Wafers with and without RTCVD Barrier Nitride Parameter Target LPCVDRTCVD Emitter Delta-w (μm) −0.02 0.01 0.04   4 × 5 μm² Joe (pA/μm²)−1.75 −1.40 −1.46 0.44 × 3 μm² Base Current (μA) 20 19.3 20.3 0.44 × 3μm² Collector Current (mA) 2 2.47 2.67 0.44 × 3 μm² Beta 100 126. 131.7  50 × 50 E-B Capacitance (fF/μm²) — 5.65 5.55   51 × 700 E-BCapacitance (fF/μm²) — 0.75 .778 4K Overall Yield (%) 75 81.5 90.6

As can be seen from the above, utilizing RTCVD nitride in place of a 200Å LPCVD nitride in the emitter process showed very good results. Theyield was improved and the electrical parameters showed little shift ascompared to the LPCVD. The small shifts experienced, if statisticallyvalid, could be corrected by photolithography adjustments or thicknessadjustments of the RTCVD nitride that are not detrimental to the processor NPN characteristics.

In the context of where a conformal nitride film is desired, the presentinvention may also be utilized. Along these lines, use of a rapidthermal chemical vapor deposition process permits deposition at highertemperatures. As a result, the present invention provides a more robustand conformal film without significant device diffusion impact thatresults from use of conventional furnace LPCVD processing. Utilizing anRTCVD process according to the present invention can produceconformalities of greater than about 90%. In some cases, theconformality may be about 95% to about 100%, when measured on bothnested and isolated structures.

An RTCVD film according to the present invention is more conformal thanLPCVD nitride films. This means that a film according to the presentinvention will fill divot structures more easily. Additionally, an RTCVDfilm according to the present invention is also more robust than LPCVDfilms. This means that films according to the present invention are lessapt to have pin-holes or other weak points where an etch might open up aleakage path between contact and substrate. The robustness of filmsaccording to the present invention is evidenced by significantly lowerwet etch rates that RTCVD nitride wet etch rates experience as comparedto PECVD nitride etch rates.

Any process for RTCVD of a nitride, but processes for forming aconformal nitride film in particular, may typically be carried out at atemperature of about 600° C. to about 800° C. Some processes accordingto the present invention may be carried out between about 700° C. andabout 775° C. Other processes according to the present invention may becarried out at temperatures of about 600° C. to about 700° C. Particularembodiments may be carried out at temperatures of about 680° C., about700° C., or about 700° C. to about 710° C.

Similarly, any process for RTCVD of a nitride, but processes for forminga conformal nitride film in particular, may typically be carried out fora period of time of about 1 minute to about 4 minutes. One particularembodiment is carried out for a time of about 95 seconds. The abovetimes are the times that the process is at a temperature wheredeposition is occurring, or substantially all of the deposition isoccurring. Some deposition may take place at lower temperatures, but thetime periods are for the time when substantially all of the depositionis occurring. It is not necessary that the time at temperature becontinuous. The temperature could be pulsed.

As described above processes according to the present invention could becarried out in a chamber such as that shown in FIG. 3. The conditionswithin the chamber can be altered to control the process for depositingthe film. Along these lines, pressure and contents of the atmospherewithin the chamber may be varied.

The pressure within a processing chamber may be from about 100 torr toabout standard pressure (760 torr). According to some embodiments, thepressure is about 250 torr or greater. Two particular embodiments employpressures of 100 torr and 250 torr. Particular pressures may be utilizedin combination with particular temperatures. Along these lines, in someembodiments, pressures of 250 torr or greater may be utilizedparticularly in combination with processing at temperatures of about600° C. to about 700° C. Similarly, in some embodiments, pressures ofabout 100 torr may be utilized in combination with processingtemperatures of above 680° C. and above.

Regarding the pressure, typically, the pressure in the processingchamber is about 70 torr to about 120 torr. More typically, the pressureis about 80 torr to about 110 torr. Most typically, the pressure isabout 100 torr.

In controlling the composition of the atmosphere within a processingchamber, various gasses may be introduced into the chamber. Along theselines, at least one nitrogen-containing gas may be introduced into thechamber. At least one silicon source gas may also be introduced into thechamber.

One example of a nitrogen source gas that may be introduced into thechamber is ammonia (NH₃). According to one embodiment, about 4 litersper minute of NH₃ gas is introduced into the processing chamber.Typically, about 3 liters per minute to about 6 liters per minute ofammonia gas may be introduced into the processing chamber. Moretypically, about 3 liters per minute to about 5 liters per minute ofammonia gas may be introduced into the processing chamber. Still moretypically, about 4 liters per minute to about 4 liters per minute ofammonia gas may be introduced into the processing chamber. Among otherfunctions, ammonia gas may be utilized to grow a nucleation layer forthe nitride deposition.

Other gasses that may be introduced into the processing chamber includesilane gas (SiN₄) and nitrogen (N₂). Typically, silane gas may beintroduced into the processing chamber at a rate of about 4 sccm toabout 60 sccm. More typically, silane gas may be introduced into theprocessing chamber at a rate of about 4 sccm to about 50 sccm. Stillmore typically, silane gas may be introduced into the processing chamberat a rate of about 4 sccm to about 20 scam. According to one particularembodiment, silane is introduced at a rate of about 40 sccm.

Other gasses that may be utilized include dichlorosilane (DCS) or any ofthe other gasses discussed above. DCS gas may be utilized in place ofSiH₄ gas to try to minimize the effect of hydrogen enhanced borondiffusion during the deposition reaction.

Additionally, deuterated gases may be deposited in order to provide adeuterated nitride to improve hot-electron performance. Along theselines, a deuterated silicon source gas may be utilized, such asdeuterated DCS or SiD₄. A deuterated nitrogen source could be providedby deuterated ammonia (ND₃). Deuterated forms of both silicon andnitrogen source gases may be used along with at least one deuteriumcarrier gas to maximize deuterium concentration in the deposited film.

According to one particular embodiment, a processing temperature ofabout 700° C. is utilized and a processing temperature of about 100torr. About 41 pm of NH₃ and about 40 sccm of SiH₄ are introduced intothe processing chamber. Nitrogen also introduced into the processingchamber according to this embodiment. When nitrogen is introduced intothe chamber, it may be introduced in more than one location. Accordingto this particular embodiment, nitrogen is introduced in a main flow andthrough a slit. The main nitrogen flow, or N₂Main, may be about 4 litersper minute. The slit flow may be about 2 liters per minute. Controllingthe two (or more) nitrogen flows relative to each other can help toimprove the uniformity of the process.

The substrate is rotated at about 40 rpm. The chamber may be heated suchthat the amount of heat directed to various regions may be controlled.Along these lines, if lamps are utilized to heat the processing chamber,the lamps may be arranged and controlled in zones. For example, thelamps may be divided into inner, outer, and lower zones. Also, the lamppower may be controlled such that it varies at different stages in theprocess. Along these lines, the process may have different values duringa heat up step, during a period of time that the process according tothe present invention is actually occurring, and during a purge stagewhen gasses are purged from the processing chamber.

Typically, the percent power levels for the lower zone/upper innerzone/lower inner zone during the heat up step are 40-70/30-60/30-60,during the process are 40-70/25-45/25-45, and during the purge step50/40/40. More typically, the percent power levels for the lowerzone/upper inner zone/lower inner zone during the heat up step are50-60/40-50/40-50, during the process are 50-60/30-40/30-40, and duringthe purge step 50/40/40. Most typically, the percent power levels forthe lower zone/upper inner zone/lower inner zone during the heat up stepare 55/45/45, during the process are 55/35/35 or 55/38/38, and duringthe purge step 50/40/40. The percentages represent percentages of thetotal lamp out power.

The deposition rate for the most typically example is about 5 Å/sec. Thedeposition time to produce a barrier nitride film having a thickness ofabout 500 Å is about 95 seconds.

According to this embodiment, the process recipe may be formatted as ahigh throughput recipe. According to this embodiment, the wafer isarranged on a hot susceptor having a temperature of about 700° C. toabout 710° C. NH₃ may then be used to grow a nucleation layer for thenitride deposition. The SiH₄ mass flow controller (MFC) may then bestabilized. Next, with SiH₄ and NH₃ flowing, the deposition occurs.After deposition, SiH₄ flow may be stopped.

However, NH₃ flow may continue for approximately 10 seconds to scavengeany available SiH₄ before the chamber is purged with N₂ and the wafer isextracted.

FIG. 7 represents a cross-sectional view of an embodiment of a nitridefilm formed according to the present invention that illustrates theposition of the barrier nitride film in standard CMOS FET construction.In FIG. 7, the conformal barrier film 48 is arranged over all of thestructures on a substrate, including silicide regions 50 and diffusionregions 52. In bipolar transistor construction, as is typically used inSiGe processing, the barrier nitride is similarly formed as the laststep to conformally cap the transistor.

FIG. 8 represents a photomicrograph of a cross-section of a PECVD filmdeposited at about 480° C. FIG. 8 shows the poor coverage of a divotarea with significant thinning in the divot area after an HF decorationof about 25 seconds. Similarly, FIG. 9 represents a photomicrograph of across-section of a PECVD film deposited at about 550° C. and illustratesthe poor coverage of a divot area with significant but slightly reducedthinning in the divot area after an HF decoration of about 25 seconds.

FIG. 10 represents a photomicrograph of a cross-section of a RTCVD filmaccording to the present invention deposited at about 700° C. FIG. 10illustrates the full coverage of a divot area with no thinning in thedivot area after an HF decoration of about 25 seconds that may beachieved according to the present invention. Along these lines, FIG. 11represents a photomicrograph of a cross-section of a RTCVD filmdeposited at about 775° C. according to the present invention. FIG. 11demonstrates the full coverage of a divot area with no thinning in thedivot area after an HF decoration of about 25 seconds that may beachieved according to the present invention.

In the context of a conformal layer, the present invention can provide abarrier nitride structure formed with a RTCVD process. A structureformed according to the present invention can conformally cover an STIdivot, at least more conformally than PECVD. A nitride film structureformed according to the present invention can resist etching moreeffectively than a PECVD deposited film. While a similar structure maybe formed using LPCVD, the LPCVD method does not integrate with CMOS orbipolar processing because of thermal budget as does the process of thepresent invention.

The structure that the processes of the present invention may deposit anitride layer on can include polycrystalline or silicon structures. Thepolycrystalline or silicon structures may have a thin oxide on them.However, the process will still work. Because the RTCVD processaccording to the present invention is a deposition process that utilizesa gaseous source of nitrogen as the nitrogen source for the nitride, itcan deposit nitride on any exposed surface. Along these lines, thepresent invention can deposit nitride on surface of poly, oxide, singlecrystal silicon, or even metal.

The foregoing description of the invention illustrates and describes thepresent invention. Additionally, the disclosure shows and describes onlythe preferred embodiments of the invention, but as aforementioned, it isto be understood that the invention is capable of use in various othercombinations, modifications, and environments and is capable of changesor modifications within the scope of the inventive concept as expressedherein, commensurate with the above teachings, and/or the skill orknowledge of the relevant art. The embodiments described hereinabove arefurther intended to explain best modes known of practicing the inventionand to enable others skilled in the art to utilize the invention insuch, or other, embodiments and with the various modifications requiredby the particular applications or uses of the invention. Accordingly,the description is not intended to limit the invention to the formdisclosed herein. Also, it is intended that the appended claims beconstrued to include alternative embodiments.

1-34. (canceled)
 35. A bipolar transistor structure, comprising: asilicon nitride barrier layer, wherein the silicon nitride barrier layerhas a conformality of greater than about 90%, and is formed by a rapidthermal nitride deposition process at a temperature from about 600° C.to about 775° C.
 36. (canceled)
 37. The transistor of claim 35, furthercomprising an insitu boron doped SiGe base.
 38. The transistor of claim35, wherein the silicon nitride barrier layer is disposed on an oxide.39. The transistor of claim 35, wherein the silicon nitride barrierlayer has a thickness from about 100 Å to about 150 Å.
 40. Thetransistor of claim 35, further comprising a polycrystalline siliconlayer adjacent to the silicon nitride barrier layer.
 41. The transistorof claim 40, wherein the polycrystalline silicon layer is capped with anitride film.
 42. The transistor of claim 35, wherein the rapid thermalnitride deposition process is performed at a temperature from about 600°C. to about 700° C.
 43. The transistor of claim 35, wherein the rapidthermal nitride deposition process is performed at a temperature fromabout 700° C. to about 775° C.
 44. The transistor of claim 35, whereinthe rapid thermal nitride deposition process is performed at atemperature from about 680° C. to about 710° C.